D16

FPGA-Master 2.0
The D16’s FPGA-Master 2.0 combines iBasso’s algorithm developments from the past three years and is central to the breakthroughs achieved in its portable discrete DAC design.

The FPGA handles signal reconstruction and processing, generating PWM signals for decoding by the subsequent PWM-DAC stage.

DAC designers recognise that once THD reaches extremely low levels, noise becomes the primary limitation to achieving greater dynamic range. The D16’s FPGA-Master 2.0 features an advanced noise shaper designed to significantly reduce the noise floor.

Global clock regeneration technology is also employed. Dual Accusilicon femtosecond oscillators provide clock references for the FPGA, which regenerates synchronised low phase-noise clocks for the DSP and USB receiver. As 1-bit DACs are highly sensitive to clock jitter, iBasso selected Accusilicon oscillators with phase noise as low as -158dBc/Hz (@1kHz). Compared to the -145dBc/Hz of standard femtosecond oscillators, phase noise is reduced by 13dB for improved jitter performance.

Picosecond-level delay control allows adjustment of I/O delay and compensation for PCB wiring delay, ensuring signals arriving at the DAC stage remain precisely aligned and synchronised.

With the precise control of FPGA-Master 2.0, 128 independent PWM-DACs operate in FIR mode to form the L+, L-, R+ and R- outputs. Each DAC data bit undergoes precise delay alignment and compensation for maximum accuracy.

Discrete PWM-DAC
After PWM signals are generated by the FPGA, they are decoded by the discrete PWM-DAC stage. The D16 employs 16 sets of cascaded E8 PWM-DACs, with four sets assigned to each of L+, L-, R+ and R-, totalling 32 PWM-DACs. This quantity exceeds that of many portable discrete DACs by more than 6.4 times. The combination of highly accurate decoding and a substantial number of premium DAC units enables THD+N performance below 0.0001%.

Hardware Analogue FIR Filter
Using FPGA-Master 2.0’s picosecond-level precision control, 128 independent PWM-DACs operate in FIR mode to create the L+, L-, R+ and R- outputs. Each channel contains 32 PWM-DACs operating in delayed parallel mode, forming a hardware analogue FIR filter. By averaging differences between multiple DACs, distortion is reduced while sound detail, density and realism are enhanced.

Super Class A Discrete Amplifier | 1125mW + 1125mW @ 32Ω
The D16 uses a similar architecture to the DX320MAX, featuring a Super Class A discrete amplifier circuit. It incorporates 20 low VCEsat (BISS) dual transistors and delivers output current capability of up to 2A, producing a powerful 1125mW + 1125mW output at 32Ω.